Cost and Investment Implications of 3D NAND

The NAND flash industry is on the cusp of a technology inflection point. 2D NAND is reaching its scaling limits with 3D NAND its anointed successor.

In the 2D NAND era, the underlying process technology (with a few exceptions) is essentially the same amongst all the NAND flash manufacturers.
However, in the 3D NAND era, all the NAND flash manufacturers are developing different 3D NAND concepts with variations in the process implementation. The different processes will impact the investment and manufacturing cost for each of the 3D NAND technologies.

This report provides a detailed analysis of the fab and manufacturing implications of 3D floating gate and charge trap NAND concepts from Samsung, Toshiba, SK Hynix and Intel-Micron versus 16nm 2D NAND. The analysis is based on a bottoms-up process flow analysis for each 3D NAND technology and 16nm 2D NAND.

Some of the questions addressed in this report include:

- What are the main drivers of the process complexity for 2D NAND and 3D NAND?
- What is the tool commonality between 3D NAND and 2D NAND?
- What is the cost impact of moving the CMOS under the array in 3D NAND?
- How much does it cost to build a Greenfield 3D NAND fab and how does it compare to a 2D NAND fab? What is the equipment footprint required and the breakdown of the investment by process modules?
- What is the front end manufacturing cost of a 3D NAND wafer compared to a 2D NAND wafer?
- What is the investment required to convert an existing 2D NAND fab to 3D NAND? What is the impact on the fab cycle time and manufacturing capacity?
- What is the incremental investment required to transition a 32 layer 3D NAND fab to 64 layers? What is the impact on fab cycle time and manufacturing capacity?

Contents
List of Figures
List of Tables
Executive Summary
Introduction
The Path to 3D
NAND Flash Technology Evolution
3D NAND Flash Memory Cell
Implementation of Floating Gate Cells into 3D NAND Flash Arrays
Floating Gate Memory Cell Scaling Challenges
Charge Trapping Memory Cell Development and Remaining Reliability Issues
Optimization of Charge Trapping Memory Cell for the Application in 3D Arrays
2D and 3D NAND Process Flow
Technology Overview and Process Challenges
3D concepts
Overview
CMOS formation
Conventional CMOS Adjacent to Memory Array
CMOS Placement Below Memory Array
3D Memory Array Formation
Toshiba p-BiCS
Samsung TCAT
3D Floating Gate
BEOL for 3D Concepts
Fundamental Limitation in 3D NAND Fabrication
2D and 3D NAND Process Comparison
Process Complexity Comparison
Cost and Investment Implications of 3D NAND
Greenfield Fab
Fab Investment
Equipment Footprint
Wafer RPT and Cycle Time
Wafer Costs
Sensitivity Analysis
Converting from 2D NAND to 3D NAND
Wafer Capacity
Investment/De-investment
3D NAND Technology Migration
Wafer Capacity
Investment/De-investment
Wafer RPT and Cycle Time
Wafer Costs
Conclusion
References
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